It’s August again, and another season at controlpaths comes to an end. This year the blog moved between very different corners of the FPGA world: from implementing AES-128 in Verilog from scratch, to getting the Agilex 3 to crunch floating-point audio filters, to chaining DSP58 slices on Versal for a single-precision biquad. I also kept digging into the security side of things, with CryptoliteICE, my open-source ring-oscillator TRNG, and closed the season by handing an AI agent the SCPI keys to my verification bench on a Red Pitaya STEMlab.

As every year, before saying goodbye until September, I want to use this last article of the season to comment on some of the news that caught my attention in the FPGA and SoC world.

Table of contents

AMD’s new Vivado/Vitis license tiers

The story that generated the most noise this season, at least in my own timeline, was the licensing overhaul that came with Vivado/Vitis 2026.1. AMD replaced the old free/paid split with a tiered model — Basic, Core and Pro as annual subscriptions, plus Enterprise and Gold as perpetual licenses for the ones who still want to own their tools instead of renting them.

The controversial part was that, in the first announcement, the free Basic tier only supported Windows. Linux, the platform every CI pipeline, every university lab and most hobbyists I know actually use, was pushed into the Core tier, priced somewhere between $1,200 and $1,800 a year. The reasoning AMD gave was that Linux was mostly used by professional users who could afford to pay. Anyone who has spent time in FPGA forums knows that is not true: a huge share of the hobbyist and open-source community runs Vivado on Linux precisely because it is the platform that plays best with scripting, version control and reproducible builds.

The backlash was immediate and loud enough — Reddit, forums, Tom’s Hardware, the usual suspects — that a few weeks later AMD reversed course and restored Linux support across all tiers, including the free Basic one. I like to think the community pressure actually worked here, and it is a good reminder that this kind of decision does get noticed.

The one genuinely good piece of news buried in this whole licensing shuffle is that, from 2026.1 onward, all 7 Series devices — Artix, Kintex, Zynq-7000 and even Virtex-7 — are included in the free Basic tier. If you only need to synthesize a small 7 Series design, Basic is now enough, no strings attached beyond the annual renewal. Given how much of my own RTL_Modules bank still targets Artix-7 boards, that is the detail I actually care about.

Microchip acquires Hailo for edge AI

Microchip signed a definitive agreement to acquire Hailo, the company behind the Hailo edge AI processor families. With this acquirement, Microchip is expanding its portfolio as they did with other acquisitions in the past.

Hailo built its reputation on dedicated AI accelerator chips for computer vision and, more recently, generative and multimodal workloads running directly on-device — cameras, drones, robotics, industrial automation. They also have real traction in the maker community through the Raspberry Pi AI Kit, which is probably the cheapest way most people have gotten their hands on a Hailo-8 so far.

Hailo-8 AI accelerator chip

Last year, we were talking about Microchip’s PolarFire Core announcement, which was about making their own FPGA line cheaper and more accessible. This year, they are taking a different approach by acquiring Hailo instead of building a competing NPU internally, which in my opinion makes sense since they are not in the high-end AI market right now, and developing one internally would take time. The question is whether they are going to integrate Hailo’s IP into their own FPGAs or keep it as a separate product line, but either way, this acquisition is a clear signal that Microchip is serious about edge AI and wants to be a player in that space.

Altera introduces the Agilex 9 Direct RF-Series

Talking about announcements, Altera announced engineering samples of the next-generation Agilex 9 Direct RF-Series, wideband SoC FPGAs aimed squarely at aerospace, defense and advanced communications systems.

In the article I wrote about the Agilex 3, I mentioned that this FPGA and SOCs from Altera offers high-end capabilities from their low-end series, but in this case we have high-end FPGAs with high-end features, which make these FPGA not for everybody, like other families from other vendors.

The journey of Altera the last years was a bit chaotic: first they seemed to be locked in their old families, then they were bought by Intel and released some new low-end families along with creating the AAgilex family, and now, since they are back to being Altera, it seems they found their way, and finally are releasing interesting families that can compete with other vendors face to face. The Agilex 9 Direct RF-Series is a good example of that, with a focus on high-performance RF and DSP applications.

For the new season I have ready some articles using the Agilex 3 SoC kit I have, which I will be publishing in the next months, and I am looking forward to seeing what other high-end families are able to do.

SEALSQ and Lattice: a unified TPM-FPGA architecture for post-quantum security

This year, I have been presenting in some conferences how FPGAs can be used to protect not only themselves, but also complete infrastructures. The key is that using FPGAs as reconfigurable HSMs, we can implement cryptographic algorithms that are not only secure, but also fast and efficient. This is especially important in the context of post-quantum cryptography (PQC), where the algorithms are more complex and require more resources than classical ones.

SEALSQ QS7001 PQC chip

Related to this, back in February, SEALSQ and Lattice announced a collaboration to bring post-quantum cryptography into Lattice’s secure FPGA lineup through a unified TPM-FPGA architecture. The proof of concept pairs a Lattice secure FPGA with SEALSQ’s QS7001, a hardware PQC chip built on a 32-bit secured RISC-V core that accelerates the NIST-selected ML-KEM (Kyber) for key encapsulation and ML-DSA (Dilithium) for digital signatures, together with the QVault TPM Root-of-Trust. They showed the demo live at Embedded World 2026 in March, at Lattice’s booth.

Conclusions

This season I have been using different FPGA families, Altera Agilex 3, Lattice ICE40, AMD Versal, Microchip PolarFire and even Effinix Trion, and I have prepared some other articles with these families, and even some boards I will release in the next months.

Regarging the FPGA industry, we can see that there are two fields where they are focusing: AI and security. The first one is clear, with the acquisition of Hailo by Microchip, and the second one is also clear, with the collaboration between SEALSQ and Lattice to bring post-quantum cryptography into Lattice’s secure FPGA lineup. Then we have Altera that is finally reaching the high-end market, and step-by-step they will be introduced in differert products.

Regarding AMD, the change in their license model is a big change, and unfortunately it is not clear if they will keep the free license for Linux users, but at least they have listened to the community and restored it for now. It is important to keep an eye on this, as it can affect the open-source community and the hobbyists that use FPGAs.

This year I’ll be again in Las Vegas at DEFCON 34, this time just attending as a visitor, but I will be looking for new FPGA-related talks and workshops. If you will be there, please come to say hello and share your thoughts about the FPGA world, and if you have any questions about the articles I wrote this season, I will be happy to answer them.

Thanks for reading, for the comments, and for pointing out the mistakes I inevitably made along the way. See you in September!